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c op y ri ght ? r d a m i c r oelec t ron i c s i nc. 2 0 0 6 . a l l ri ght s a re re s e r v e d. th e information contained herein is the exclusive property of rda and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of rda . rda580 7m s ingle - c hip b ro a dca st fm r a dio t un er rev .1.0 C may .2 0 1 1 1 g e ner a l des c ription t h e r da 5 80 7m series is the new est generation single - chip broadcast fm stereo radio tuner with fully integrated synthesizer, if selectivity , rds/rbds and mpx de coder. the tuner uses the cmos process, support multi - interface and require the least external component. all these make it very suitable for portable devices. t h e rda 58 07 m series has a powerful low - if digital audio processor, this make it have optimum sou nd quality with varying reception conditions. t h e r da 58 07 m series support frequency range is from 50 mhz to 11 5mhz. 1.1 f ea t u r es ? c m o s single - chip fully - integrated fm tuner ? l o w p ower consumption ? t o t a l c u r r e n t c o n s u m p t i o n l o w e r t h a n 2 0 m a a t 3 . 0 v p o w e r s upply w hen under normal situation ? s u p p o rt worldwide frequency band ? 50 - 1 15 mhz ? sup p o r t f l e x i b l e c h a n n e l s p a c i n g m o d e ? 1 0 0 k h z, 200khz, 50khz and 25khz ? s u p p o rt rds/rbds ? d i g i t al low - if tuner ? i m a g e - reject down - converter ? h i g h performance a/d converter ? i f s e lectivity pe rformed internally ? f u l l y integrated digital frequency synthesizer ? f u l l y integrated on - chip rf and if vco ? f u l l y integrated on - chip loop filter ? a u t o n omous search tuning ? s u p p o rt 32.768khz crystal oscillator ? d i g i t al auto gain control (agc) ? d i g i t al adaptive noi se cancellation ? m o n o / stereo switch ? s o f t mute ? h i g h cut ? p r o g r ammable de - emphasis (50/75 ? s) ? r e c e i ve signal strength indicator (rssi) and snr ? b a s s boost ? v o l u m e control and mute ? l i n e - level analog output voltage ? 3 2 . 7 6 8 khz 12m,24m,13m,26m,19.2m,38.4mhz r e f e r e n c e c l o c k ? o n l y support 2 - wire bus interface ? d i r e c tly support 32 resistance loading ? i n t e g rated ldo regulator ? 1 . 8 t o 3.3 v operation voltage ? msop 10 pin s 1 . 2 ap p l ications ? c e l l u lar handsets ? m p 3 , mp4 players ? p o r t a ble radios figure1 - 1. rd a 5807m top view 6 7 8 9 10 1 2 3 4 5 rda 5807 m lo ut ro ut g nd v dd rclk g nd fmin g nd s clk s dio http://
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 2 of 23 ? pdas, noteboo k
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 3 of 23 table of contents 1 general description ................................ ................................ ................................ ................................ .... 1 1.1 features ................................ ................................ ................................ ................................ ......... 1 1. 2 applications ................................ ................................ ................................ ................................ .... 1 table of contents ................................ ................................ ................................ ................................ ................. 3 2 functional description ................................ ................................ ................................ ................................ 4 2.1 fm receiver ................................ ................................ ................................ ................................ .. 4 2.2 synthesizer ................................ ................................ ................................ ................................ .... 4 2.3 power supply ................................ ................................ ................................ ................................ 4 2.4 reset and control interface s elect ................................ ................................ ............................. 5 2.5 control interface ................................ ................................ ................................ ........................... 5 3 electrical characteristics ................................ ................................ ................................ ........................... 6 4 receiver characteristics ................................ ................................ ................................ ............................. 7 5 serial interface ................................ ................................ ................................ ................................ ............ 8 5.1 i 2 c interface timing ................................ ................................ ................................ ...................... 8 6 register definition ................................ ................................ ................................ ................................ ...... 9 7 pins description ................................ ................................ ................................ ................................ ......... 14 8 application diagram ................................ ................................ ................................ ................................ . 16 8.1 rda 5807m common application : ................................ ................................ ........................... 16 8.1.1 bill of materials: ................................ ................................ ................................ ......................... 17 9 physical dimension ................................ ................................ ................................ ................................ ... 18 10 pc b land pattern ................................ ................................ ................................ ................................ ..... 19 change list ................................ ................................ ................................ ................................ ........................ 22 11 notes ................................ ................................ ................................ ................................ ....................... 22 12 c onta ct information ................................ ................................ ................................ ................................ . 23
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 4 of 23 2 functional description figure 2 - 1 . rda 5807m fm tuner block diagram 2.1 fm receiver t he r ec ei v er us es a di gi tal l o w - if arc h i tec ture th at av o i ds t he di f f i c ul t i es a s s oc i ate d wi t h d i r ec t c on v ers i on w h i l e de l i v er i n g l o wer s ol ut i on c os t an d r ed uc es c om pl ex i t y , an d i n teg r a tes a l o w no i s e am pl i f i er ( lna ) s up po r ti ng the f m broadc as t b an d ( 50 t o 1 15 mh z ) , a m ul ti - ph as e i m ag e- r ej ec t m i x er arr a y , a pro gram m ab l e ga i n c on tr ol ( p g a ) , a h i gh r es o l ut i on an al o g - to - d i gi tal c on v ert ers ( a dcs ) , an au di o d s p an d a h i gh - f i de l i t y di gi t a l - to - a na l og c o n v erter s ( da cs ) . t he l i m i ter pre v e nt s o v er l oa d i ng a nd l i m i t s the am ou nt of i nte r m od ul a ti o n produc t s c r ea t ed b y strong adjacent channels. t he m ul ti - ph as e m i x er arr a y do w n c on v ert s th e ln a ou t pu t di f f erenti al rf s i gn a l to l o w - if , i t a l s o ha s i m ag e - r ej ec t f un c ti o n an d h arm on i c ton es rejection . t he p g a am pl i f i es the m i x er ou t pu t if s i gn al an d the n di gi t i z ed wi th a dcs . t he ds p c ore f i n i s he s t he c ha nn e l s e l ec t i on , f m de m od ul at i on , s tereo mp x de c od er a nd o utp ut au d i o s i gn a l . t he m p x de c od er c an au t on om ou s s w i tc h f r om s tereo to m on o t o l i m i t t he ou tpu t no i s e. t he dacs convert digi tal audio signal to analog and change the volume at same time. the dacs has low - pass feature and - 3db frequency is about 30 khz . 2.2 synthesizer t he fr eq ue nc y s y nth es i z e r ge ne r at es the l oc al os c i l l ato r s i gn a l w h i c h di v i d e to m ul ti - p ha s e , t he n be us e d t o d o w nc o nv ert the rf i np ut t o a c on s t an t l o w i nt erm ed i ate f r eq ue nc y ( if) . t he synthesizer reference clock is 32.768 khz . t he s y nth es i z er f r eq ue nc y i s de f i ne d b y bi t s chan [ 9:0 ] wi t h the r an ge f r o m 50 mh z to 1 15 mh z . 2.3 power supply t he rda 58 07 m i nt eg r at ed on e ldo w h i c h suppl ies power to the chip. t he external supply voltage range is 1.8 - 3.3 v. i a d c l d a c r d a c q a d c + - a u d i o d s p c o r e d i g i t a l f i l t e r m p x d e c o d e r s t e r e o / m o n o a u d i o v c o s y n t h e s i z e r i n t e r f a c e b u s r s s i v i o s d i o s c l k m c u r d a 5 8 0 7 m l o u t r o u t f m _ i n r c l k 2 . 7 - 3 . 3 v 3 2 . 7 6 8 k h z v d d l d o l i m i t e r l n a i p g a q p g a r d s / r b d s
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 5 of 23 2.4 reset and control interface select t he rda 58 07 m i s re s e t i t s el f w he n v io i s p o w er up . a nd al s o s u pp o r t s oft r es et b y tr i g ge r 02h bit1 from 0 to 1 . t he rda 5807m only support i 2 c control interface bus mode. 2.5 control interface t he rda 58 0 7m o nl y s up po r t s i 2 c c on tr o l i nte r f ac e. t he i 2 c i nte r f ac e i s c o m pl i an t to i 2 c b us s pe c i f i c at i o n 2.1 . i t i nc l ud e s tw o p i ns : s cl k an d s dio . a i 2 c i nt erf ac e tr an s f er be gi ns wi th s t a r t c on di t i o n, a c o m m an d b y t e an d da ta b y t es , ea c h b y t e h as a f ol l o wed a c k ( o r na c k ) bi t, a nd en ds wi th s t o p c on d i ti on . t he c om m an d b y te i nc l ud e s a 7 - bi t c h i p a dd r es s ( 00 1 0 00 0b ) a nd a r / w bi t. t he a c k ( or na c k ) i s al wa y s s e nt ou t b y r ec e i v er . w h en i n w r i t e tr an s f er , d ata b y t es i s w r i tte n ou t from mcu, and when in read transfer, data bytes i s read out from rda 5807m . there is no visible register address in i 2 c interface transfers. the i 2 c interface has a fixed start register address ( 0x 02h for write transfer and 0x 0ah for read transfer), and an internal incremental address counter. if register address meets the end of register file, 0x 3a h, register address will wrap back to 0x 00h. for write transfer, mcu programs registers from register 0x 02h high byte, then register 0x 02h low b yte, then register 0x 03h high byte, till the last register. rda 5807m always gives out ack after every byte, and mcu gives out stop condition when register programming is finished. for read transfer, afte r command byte from mcu, rda 5807m sends out register 0x 0ah high byte, then register 0x 0ah low byte, then register 0x 0bh high byte, till receives nack from mcu. mcu gives out ack for data bytes besides last data byte. mcu gives out nack for last data byte, and then rda 5807m will return the bus to mcu, and mcu will give out stop condition.
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 6 of 23 3 electrical characteristics table 3 - 1 dc electrical s pecification (recommended operation conditions): symbol description min typ max unit vdd supply voltage 1.8 3. 0 3.3 v t amb ambient temperature - 2 0 2 7 +7 5 v il cmos low level input voltage 0 0.3*v io v v ih cmos high level input voltage 0.7*v io v io v v th cmos threshold voltage 0.5* vio v table 3 - 2 dc electrical specification (absolute maximum ratings): s ymbol description min typ max unit vio interface supply voltage - 0.5 + 3.3 v t amb ambient temperature - 40 +90 c i in input current (1) - 10 +10 ma v in input voltage (1) - 0.3 vio+0.3 v v lna lna fm input leve l +10 dbm notes: 1. for pin: sclk, sdio t able 3 - 3 power c onsumption s pecification (v dd = 3 v, t a = 25 , unless otherwise specified) symbol description condition typ unit i vdd supply current (1) enable=1 20 ma i vdd supply current (2 ) enable=1 2 1 ma i vio interface supply current sclk and rclk active 6 0 ? a i pd powerdown current enable=0 5 ? a i vio interfa ce powerdown current enable=0 10 ? a notes: 1. for strong input signal condition 2. for weak input signal condition
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 7 of 23 4 receiver characteristics table 4 - 1 receiver characteristics ( v dd = 3 v , t a = 25 c, unless otherwi se specified) symbol parameter conditions min typ max unit general specifications f in fm i nput f requency range adjust band register 50 115 mhz v rf sensitivity 1,2,3 s /n=26db 50 mhz - 1 .4 1. 8 ? v emf 65 mhz - 1.2 1.5 88mhz - 1.2 1.5 98mhz - 1. 3 1.5 108mhz - 1.3 1.5 115mhz - 1.3 1. 8 ip3 in input ip3 4 agcd=1 80 - - db ? v am a m suppression 1,2 m = 0.3 60 - - db s 200 adjacent channel selectivity 200khz 50 70 - db s 400 400khz selectivity 400khz 60 85 - db v afl ; v afr audio l/r output vo ltage 1,2 (pins lout and rout) volume [3:0] =1111 - 36 0 - mv s/n maximum signal to noise ratio 1,2,3,5 mono 2 55 57 - db stereo 6 53 55 - scs stereo channel separation 35 - - db r l audio output loading resistance single - ended 32 - - thd audio tot al harmonic distortion 1,3,6 volume [3:0] =1111 r load =1k - 0. 15 0. 2 % r load =32 - 0.2 - aoi audio output l/r imbalance 1,6 - - 0. 05 db r mute mute attenuation ratio 1 volume[3:0]=0000 60 - - db bw audio audio response 1 1khz=0db 3 db point low freq 9 - 10 0 - hz high freq - 14 - pins fm_in , lout, rout v com_rfin pins fm_in input common mode voltage 0 v v com audio output common mode voltage 8 1.0 1. 05 1. 1 v no tes: 1. f in =6 5 to 1 15 mhz; f mod =1khz; de - emphasis=75 ? s; mono=1; l=r unless noted otherwise ; 2 . ? f=22.5khz ; 3. b af = 300hz to 15khz, rbw <=10hz; 4. |f 2 - f 1 |>1mhz, f 0 =2xf 1 - f 2 , agc disable, f in = 76 to 108mhz ; 5. p rf =60db u v; 6. ? f= 7 5kh z , f pi l ot = 10% 7. measured at v emf = 1 m v, f rf = 65 to 108mhz 8. at lout a n d rout pi n s 9. adj u s t a bl e
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in p a r t w it h o u t p r ior w r it t e n p e r m i s s io n o f r d a . page 8 of 23 5 serial interface 5.1 i 2 c interface t iming table 5 - 1 i 2 c interface t iming c haracteristics ( v dd = 3 v , t a = 25 c, unless otherwise specified) parameter symbol test condition min typ max unit sclk frequency f scl 0 - 400 khz sclk high time t high 0.6 - - ? s sclk low time t low 1.3 - - ? s setup time for start condition t su:sta 0.6 - - ? s hold time for start condition t hd:sta 0.6 - - ? s setup time for stop c ondition t su:s to 0.6 - - ? s sdio input to sclk setup t su:dat 100 - - ns sdio input to sclk hold t hd:dat 0 - 900 ns stop to start time t buf 1.3 - - ? s sdio output fall time t f:out 20+0.1c b - 250 ns sdio input, sclk rise/fall time t r:in / t f:in 20+0.1c b - 300 ns input spike suppression t sp - - 50 ns sclk, sdio capacitive loading c b - - 50 pf digital input pin capacitance 5 pf figure 5 - 1 . i 2 c interface write timing diagram figure 5 - 2 . i 2 c int erf ac e re ad t i m i ng di ag r am s c l k s d i o 1 - 7 8 9 1 - 7 8 9 1 - 7 8 9 s t a r t a c k d a t a h i g h b y t e a c k r / w a d d r e s s d a t a l o w b y t e a c k s t o p t s u : s t a t h d : s t a t s p s t a r t t s u : s t o t b u f t s u : d a t t h d : d a t s c l k sd i o 1- 7 8 9 1- 7 8 9 1- 7 8 9 s t a r t a c k d a t a h i g h b y t e a c k r / w a d d r e s s d a t a l o w b y t e n a c k s t o p t s p s t a r t t b u f t su : st a t h d: st a t su : d a t t h d: d a t t s u : s t o
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 9 of 23 6 register definition reg bits name function default 00h 15:8 chipid[7:0] chip id. 0x 58 02h 15 dhiz audio output high - z disable. 0 = high impedance; 1 = normal operation 0 14 dmute mute d isable. 0 = mute; 1 = normal operation 0 13 mono mono select. 0 = stereo; 1 = force mono 0 12 bass bass boost. 0 = disabled; 1 = bass boost enabled 0 11 rclk n on - calibrate mode 0=rclk clock is always supply 1=rclk clock is not always supply when fm w ork ( when 1, rda 5807m can t directly support - 20 ~70 temperature. only suppory 20 temperature swing from tune point ) 0 10 rclk direct input mode 1=rclk clock use the directly input mode 0 9 seekup seek up. 0 = seek down; 1 = seek up 0 8 seek seek. 0 = disable stop seek ; 1 = enable seek begins i n the direction specified by seekup and ends when a channel is found, or the entire band has been searched. the seek bit is set low and the stc bit is set high when the seek operation completes. 0 7 skmode seek mode 0 = wrap at the upper or lower band l imit and continue seeking 1 = stop seeking at the upper or lower band limit 0 6:4 clk_mode[2:0] 000=32.768khz 001=12mhz 101=24mhz 010=13mhz 110=26mhz 011=19.2mhz 111=38.4mhz 000 3 rds_en rds/rbds enable i f 1, rds/rbds enable 0 2 new_method new demodu late method enable, can improve the receive sensitivity about 1db. 0 1 soft_reset soft reset. if 0, not reset; if 1, reset. 0
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 10 of 23 reg bits name function default 0 enable power up enable. 0 = disabled; 1 = enabled 0 03h 15: 6 chan[ 9 :0] channel select. band = 0 frequency = channel spacin g (khz) x chan + 87 .0 mhz band = 1 or 2 frequency = channel spacing (khz) x chan + 76.0 mhz band = 3 frequency = channel spacing (khz) x chan + 6 5 .0 mhz chan is updated after a seek operation. 0x00 5 direct mode directly control mode, only used when test. 0 4 tune tune 0 = disable 1 = enable the tune operation begins when the tune bit is set high. the stc bit is set high when the tune operation completes. the tune bit is reset to low automatically when the tune operation completes.. 0 3: 2 band[1:0] ban d select. 00 = 87 C 108 mhz (us/europe) 01 = 76 C 91 mhz (japan) 10 = 76 C 108 mhz ( world wide) 11 1 = 65 C 76 mhz east europe or 50 - 6 5 m h z 0 0 1: 0 space [1:0] channel spacing. 00 = 100 khz 01 = 200 khz 10 = 50khz 11 = 25khz 0 0 04h 15 rsvd reserved 0 13:12 rsvd reserved 00 11 de de - emphasis. 0 = 75 s; 1 = 50 s 0 10 rsvd reserved 9 softmute_en if 1, softmu te enable 1 8 afcd afc disable. if 0, afc work; if 1, afc disabled. 0 05h 15 int _mode if 0, generate 5ms interrupt; if 1, interrupt last until read reg0 c h action occurs. 1 1 if 0x07h_bit<9> ( band )=1, 65 - 76mhz; =0, 50 - 76mhz
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 11 of 23 reg bits name function default 14:12 rsvd reserved 000 1 1 :8 seekth[3 :0] 2 seek snr threshold value 1000 5 :4 rsvd resvered 0 0 3:0 volume[3:0] dac gain control bits (volume). 0000=min; 1111=max volume scale is logarithmic when 0000, output mute and output impedance is very large 1111 06h 15 rsvd reserved 0 14 :13 open_mode [ 1:0 ] open reserved register mode. 11=open behind registers writing function others: only open behind registers reading function 0 0 07h 15 rsvd reserved 0 14:10 th_sofrblend[5:0] threshold for noise soft blend setting, unit 2db 10000 9 65m_50m mode valid when band[1:0] = 2b11 (0x03h_ bit<3:2>) 1 = 65~76 mhz; 0 = 50~76 mhz. 1 8 rsvd reserved 0 7:2 seek_th _old 3 seek threshold for old seek mode , valid when seek_mode=001 000000 1 softblend_en if 1, softblend enable 1 0 freq_mode if 1, then freq setting changed. freq = 76000(or 8700 0) khz + freq_direct (08h) khz. 0 0ah 15 rdsr rds ready 0 = no rds/rbds group ready(default) 1 = new rds/rbds group ready 0 14 stc seek/tune complete. 0 = not complete 1 = complete the seek/tune complete flag is set when the seek or tune operation compl etes. 0 13 sf seek fail. 0 = seek successful; 1 = seek failure the seek fail flag is set when the seek operation fails to find a channel with an rssi level greater than seekth[5:0] . 0 12 rdss rds synchronization 0 = rds decoder not synchronized(default ) 1 = rds decoder synchronized available only in rds verbose mode 0 11 blk_e when rds enable: 0 2 this value is snr threshold for seeking, and the default value 1000 is about 32db snr. 3 0x20h_bit<14:12>, seek_mode register . default value is 000; when = 001, will add the 5802e seek mode.
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 12 of 23 reg bits name function default 1 = block e has been found 0 = no block e has been found 10 st stereo indicator. 0 = mono; 1 = stereo 1 9:0 readchan[9:0] read channel. band = 0 frequency = channel spacing (khz) x readchan[9:0]+ 87.0 mhz band = 1 or 2 frequency = channel spacing (khz) x readchan[9:0]+ 76.0 mhz band = 3 frequency = channel spacing (khz) x readchan[9:0]+ 65.0 mhz readchan[9:0] is updated after a tune or seek operation. 8h0 0 0bh 15:9 rssi[6:0] rssi. 000000 = min 111111 = max rssi scale is logarithmic. 0 8 fm true 1 = the current channel is a station 0 = the current channel is not a station 0 7 fm_ready 1=ready 0=not ready 0 <6:5> reserved 0 <4> abcd_e 1= the block id of register 0ch,0dh,0eh,0fh is e 0= the block id of register 0ch, 0dh, 0eh,0fh is a, b, c, d <3:2> blera[1:0] b l ock e rrors lev e l of r d s _ d a t a _ 0 , a nd i s always read as errors level of rds block a (in rds mode) or block e (in rbds mode when abcd_e fla g is 1) 00= 0 errors requiring correction 01= 1~2 errors requiring correction 10= 3~5 errors requiring correction 11= 6+ errors or error in checkword, correction not possible. available only in rds verbose mode <1:0> blerb[1:0] block errors level of rds _data_1, and is always read as errors level of rds block b (in rds mode ) or e (in rbds mode when abcd_e flag is 1). 00= 0 errors requiring correction 01= 1~2 errors requiring correction 10= 3~5 errors requiring correction
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 13 of 23 reg bits name function default 11= 6+ errors or error in checkwo rd, correction not possible. available only in rds verbose mode 0ch <15:0> rdsa[15:0] block a ( in rds mode) or block e (in rbds mode when abcd_e flag is 1) 16 h5803 0dh <15:0> rdsb[15:0] block b ( in rds mode) or block e (in rbds mode when abcd_e flag is 1) 16 h5804 0eh <15:0> rdsc[15:0] block c ( in rds mode) or block e (in rbds mode when abcd_e flag is 1) 16 h5808 0fh <15:0> rdsd[15:0] block d ( in rds mode) or block e (in rbds mode when abcd_e flag is 1) 16 h5804
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 14 of 23 7 p in s des c ription figure 7 - 1 . rda 5807m top view table 7 - 1 rda 5807m pins description symbol pin description gnd 1,3,8 ground. connect to ground plane on pcb fm_in 2 lna dual input port. rclk 6 32 .768khz crystal oscillator and r eference clock input sdio 5 d ata i np ut/output for serial control bus s c lk 4 clock input for serial control bus vdd 7 power supply r o u t , l o u t 9 , 10 right/left audio output 6 7 8 9 1 0 1 2 3 4 5 r d a5 8 0 7 m l o u t r o u t g n d vd d r c l k g n d f m i n g n d sc l k sd i o
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 15 of 23 table 7 - 2 internal pin configuration symbol pin description fm_in 2 rclk 6 sdio / sclk 5 / 4 l n a p f m s m n 1 r l o a d 5 0 p f r c l k 5 m 2 0 p f 6 p f i n v 5 m 0 x 0 2 h _ b i t < 1 0 > v d d = 1 = 0 4 7 k s i n s o u t m n 1 s d i o \ s c l k
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 16 of 23 8 application d iagram 8.1 audio loading resistance larger t han 32 & tcxo application : figure 8 - 1 . RDA5807M fm tuner application diagram ( tcxo application ) 8.1.1 bill of materials: component value description supplier u1 RDA5807M broadcast fm radio tuner rda j1 common 32 resistance headphone l 1 / c 1 100nh/ 22 pf lc cho ck fo r fm_in input murata c3 ,c 4 125 f audio ac couple capacitors murata c 2 2 2 nf power supply bypass capacitor murata f1/f2 1.5k@100mhz fm band ferrite murata notes: 1. j1: common 32? resistance headphone ; 2. u1: RDA5807M chip ; 3 . v1: power supply ( 1.8 ~ 3.3 v) ; 4 . fm choke (l 1 and c 1 ) for audio common and lna input c ommon ; 5. place c2 close to 5807m pin 7. j 1 r c l k s c l k s d i o v 1 c 4 1 2 5 u f c 3 1 2 5 u f c 2 2 2 n f 6 7 8 9 1 0 1 2 3 4 5 l o u t r o u t g n d v d d r c l k g n d f m i n g n d s c l k s d i o r d a 5 8 0 7 m l 1 1 0 0 n h c 1 2 2 p f u 1 f 1 1 . 5 k @ 1 0 0 m h z f 2 1 . 5 k @ 1 0 0 m h z
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 17 of 23 8.2 audio loading resistance l ower t han 32 & dcxo application : f igure 8 - 2 . rda580 7m fm tuner application diagram ( 32.768k crystal) 8.2.1 bill of materials: component value description supplier u1 rda 5807m broadcast fm radio tuner rda j1 common 32 resistance headphone l 1 / c 1 100nh/ 22 pf lc chock fo r fm_in input murata c3 ,c 4 125 f audio ac c ouple capacitors murata c 2 2 2 nf p o w er supply bypass capacitor murata f1/f2 1.5k@100mhz fm band ferrite murata notes: 1. j1: common 32? resistance headphone ; 2. u1: rda 5807m chip ; 3 . v1: power supply ( 1.8 ~ 3.3 v) ; 4 . fm choke (l 1 and c 1 ) for audio common and lna input c ommon ; 5 . place c2 close to 5807m pin 7 . j 1 sclk s d i o v 1 c 4 125 u f c 3 125 u f c 2 22 n f 6 7 8 9 1 0 1 2 3 4 5 l o u t r o u t g n d vd d r c l k g n d f m i n g n d sc l k sd i o r d a 5 8 0 7 m l 1 1 0 0 n h c 1 2 2 p f u 1 f 1 1 . 5 k @ 100 m h z f 2 1 . 5 k @ 100 m h z 3 2 . 7 6 8 k
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 18 of 23 9 physical dimension figure 9 - 1 illustrates the package details for the rda 5807m . the pack age is lead - free and rohs - compliant. figure 9 - 1 . 10 - pin msop
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 19 of 23 10 pcb land pattern fig ure 10 - 1 . classification reflow profile profile feature sn - pb eutectic assembly pb - free assembly average ramp - up rate (t smax to t p ) 3 o c/second max. 3 o c/second max. preheat - temperature min (t smin ) - temperature max (t smax ) - time (t smin to t smax ) 100 o c 100 o c 60 - 120 seconds 150 o c 200 o c 60 - 180 seconds time maintained above: - temperature (t l ) - time (t l ) 183 o c 60 - 150s econds 217 o c 60 - 150 seconds peak /classification temperature(t p ) see table - ii see table - iii time within 5 o c of actual p ea k t e m pe r atu r e ( t p ) 10 - 30 seconds 20 - 40 seconds ramp - down rate 6 o c/second max. 6 o c/seconds max. time 25 o c to peak temperature 6 minutes max. 8 minutes max. table - i classification reflow profiles
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 20 of 23 package thickness volume mm 3 <350 volume mm 3 350 2.5mm 240 + 0/ - 5 o c 225 + 0/ - 5 o c 2.5mm 225 + 0/ - 5 o c 225 + 0/ - 5 o c table C ii snpb eutectic process C package peak reflow temperatures package thickness volume mm 3 350 volume mm 3 350 - 2000 volume mm 3 2000 1.6mm 260 + 0 o c * 260 + 0 o c * 260 + 0 o c * 1.6mm C 2.5mm 260 + 0 o c * 250 + 0 o c * 245 + 0 o c * 2.5mm 250 + 0 o c * 245 + 0 o c * 245 + 0 o c * * tolerance : the device manufacturer /supplier shall assure process compatibility up to and including the stated classification temperature(this mean peak reflow temperature + 0 o c. for example 260+ 0 o c ) at the rated msl level. t ab l e C i i i p b - f ree p roce ss C p ac ka ge c l as sif i ca t i on r e f l o w t empe rat u res note 1: all temperature refer topside of the package. m easured on the package body surface. n ote 2: t he pro f i l i ng t ol erance i s + 0 o c , - x o c ( ba sed o n m ach i ne v aria t i o n cap ab i l i t y ) w ha t ev er i s r e q ui r ed t o c on t r ol t he pro f i l e pro ces s bu t a t no t i m e w i l l i t ex cee d - 5 o c . t h e produce r assu r es p r oce s s co m pa t i bi l i t y at t he pe a k r e f l ow pro f i l e t e m pe r a t ures de f i n e d i n t ab l e C i i i . note 3: package volume excludes external terminals(balls , bumps, lands, leads) and/or non integral heat sinks. note 4: the maximum component temperature reached during reflow depends on package the thickness and volume. the use of convection reflow processes reduces the thermal gradients between packages. howev er, thermal gradients due to differences in thermal mass of smd pack age may sill exist. note 5: components intended for use in a lead - free assembly process shall be evaluated using the lead free classification temperatures and profiles defined in table - i ii iii whether or not lead free.
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 21 of 23 rohs compliant the product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (pbb) or polybrominated diphenyl ethers (pbde) , and are therefore considered rohs compliant. esd se nsitivity integrated circuits are esd sensitive and can be damaged by static electricity. proper esd techniques should be used when handling these devices.
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 22 of 23 change list rev date auther change description v 1.0 20 11 - 0 5 - 2 3 chun zhao original d raft . 11 notes
rda mi c r o el ec tr o ni c s , in c . r da 5807m f m t u n e r v 1 .0 the in f o r m a t ion c o n t a ine d h e r e in i s t h e e x c lus iv e p r o p e r t y o f r d a a n d s h a l l n o t b e d i s t r ibu t e d , r e p r o d u c e d , o r d is c lo s e d in w h o le o r in part without prior written permission of rda . page 23 of 23 12 contact information rda m icroelectronics ( shanghai), inc. suite 1108 block a, e - wing center, 113 zhichun road haidian district, beijing t el : 86 - 10 - 6 26 3 53 6 0 f ax : 86 - 10 - 8 26 1 26 6 3 postal code: 100086 suite 302 building 2, 6 90 bibo road pudong district, shanghai t el : 86 - 21 - 5 02 71 10 8 f ax : 86 - 21 - 5 02 7 10 9 9 postal code: 201203 copyright ? rda microelectronics inc. 2006. all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

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